Resume

Profile

Computer Engineering senior at Johns Hopkins University (graduating May 2027) focused on RTL design, design verification, and FPGA/ASIC engineering. Experience spans FPGA protocol design in VHDL, low-level C/C++ systems work, and student leadership as Co-President of the JHU chapter of the National Society of Black Engineers. U.S. Citizen.

Looking for: full-time roles in RTL design, design verification, FPGA, and embedded engineering, starting after I graduate in May 2027. I'm open to relocating and to other opportunities for hands-on hardware experience.

"Morgan successfully navigated the challenge with distinction... his continued learning outside the classroom speaks volumes about his grit, determination, and passion for self-directed learning. I firmly believe Morgan will prove an asset to any team."
— Brennon Brimhall, Instructor & Researcher, Johns Hopkins University

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Education

B.S. Computer Engineering

Expected May 2027 at Johns Hopkins University, Baltimore, USA

FPGA Lab Computer System Fundamentals Signals & Systems Mastering Electronics Robots, Sensors & Actuators Computer Vision Data Structures

Engineering Math, Marketing Fundamentals for Media

Jan 2022 to Jun 2023 at Lethbridge College (online)

Introduction to Business Management

Sep 2021 to Dec 2021 at Southern Alberta Institute of Technology (online)

Experience

Software Engineering Intern (Edge Software Optimization) at Morgate Solutions

Jun 2026 to Aug 2026

• Containerized C/C++ parsers with Docker for Linux edge gateways, optimizing memory use to fit 512 MB device limits
• Emulated network jitter and profiled CPU usage to find and prevent buffer overflows in high-frequency data streams

Data Science Researcher at #iVoted Impact Concerts, SNF Agora Institute

May 2025 to May 2026

• Processed music-listener and voter-demographic data from RedistrictingDataHub & Geocorr APIs
• Automated weekly ETL workflows with Python and the Google Sheets API
• Maintained dashboards that projected concert-driven voter registrations

Software Engineering Intern (Low-Level Data & Protocol Bridging) at Morgate Solutions

Jun 2024 to Aug 2024

• Developed C extraction tools using struct packing and bitwise operations to decode 50+ GB of binary telemetry
• Managed struct byte alignment and endianness; built a Python test harness to validate parser output

Robotics Designer at VEX Robotics

Nov 2019 to Mar 2023

• Designed & programmed competition robots in C++ / Python
• Integrated sensors, tuned motor controllers, and produced CAD for 3-D-printed parts
• Diagnosed mechanical/electrical issues and iterated designs

Leadership

Co-President at National Society of Black Engineers, JHU Chapter

Sep 2023 to Present (previously Vice President and Finance Chair)

• Secured sponsorships from Medtronic, Visa, and Jane Street; hosted events with Medtronic and Shift Alt Her
• Grew reach through events with JHU's Life Design Lab and Pava Center and collaborations with five student organizations, including SHPE and BMES
• Building the chapter website; grew outreach on Instagram and LinkedIn and started alumni LinkedIn and WhatsApp groups
• Delegate committee work, run fundraisers and logistics, and fund member travel to regional and national conferences
• As Finance Chair, managed a $9K annual budget and secured $3.5K through fundraising and corporate sponsorships

Fundraising Chair at HopThon, JHU Dance Marathon

Fall 2025 to Spring 2026

Philanthropy Chair at Alpha Epsilon Pi

Spring 2025

Skills

VHDL Verilog Verilator Xilinx Vivado (Synthesis, Place and Route) Self-Checking Testbenches LTSpice Oscilloscope Multimeter C/C++ Arduino Python (NumPy, Pandas, Matplotlib) MATLAB Bash Linux (Ubuntu) Git Docker GenAI Tools (Claude, Gemini, Cursor) SystemVerilog (Learning) SystemC (Learning)

Foundational Concepts

Digital design and RTL, FSM design, clock domain crossing (CDC) with two-flop synchronizers for asynchronous inputs, UART, I²C and SPI protocol implementation, open-drain I/O, microcontroller firmware, circuit analysis, analog and digital (continuous- and discrete-time) signals, cache and memory hierarchy, binary data formats (struct packing, endianness), and basic x86-64 assembly.