Hey there 👋

I'm Morgan Huberty

Computer Engineering Student

Welcome to my personal website and digital portfolio! I'm a senior at Johns Hopkins University studying Computer Engineering (graduating May 2027), focused on RTL design, design verification, and FPGA/ASIC engineering.

Looking for: full-time roles in RTL design, design verification, FPGA, and embedded engineering, starting after I graduate in May 2027. I'm open to relocating and to other opportunities for hands-on hardware experience.

Download Resume

Education 🎓

Johns Hopkins University

Academic Focus 📚

My major-relevant interests include:

RTL Design & Design Verification
Computer Architecture
FPGA Prototyping & Hardware Bring-Up
ASIC Design Flow
Hardware for AI Acceleration
The Semiconductor Industry & Supply Chain

Personal Interests 🧐

Beyond my academic pursuits, I'm passionate about:

Health & Longevity
History
Resistance Training
Philosophy
Classic Novels
Cooking
Pop Culture
Sailing
Nature Walks

Thanks for stopping by! 🎉

Exploring the tight interplay between software and hardware.

Hardware Design

ZipCPU Soft-Core Processor Build (Verilog)
In Progress

Working through the ZipCPU tutorial curriculum toward building a 32-bit pipelined RISC soft-core processor on an Artix-7 FPGA. Simulating each design with Verilator and C++ test drivers, then validating it on hardware.

UART Transceiver (VHDL)

Designed a UART transmitter and receiver (8N1, 115,200 baud from a 12 MHz clock) with FSM control, a two-flop RX synchronizer, and mid-bit sampling. Verified with a self-checking testbench, then on hardware via loopback.

I²C Master Controller (VHDL)

Designed an FSM-based I²C master with repeated start, ACK/NACK, clock stretching, and open-drain SDA/SCL via Xilinx IOBUF primitives. Validated end-to-end on hardware with a PIC16F18326 slave.

Software Systems

Key/Value Store (C++)

Built a Redis-like in-memory K/V store with custom message serialization, multithreaded server (auto-commit & transactions with table-level locking), client utilities, and unit tests.

Cache Simulator (C, C++)

Simulated a configurable set-associative cache (sets, blocks, block size, LRU/FIFO replacement, write policies) that reports hit/miss counts and cycle totals from memory traces, used to compare associativity and policy trade-offs.